Abstract: Five-level inverters can reduce the voltage stress on switching devices, but suffer from DC-link capacitor voltage imbalance issue. Existing modulation schemes balance DC-link capacitor voltages by introducing additional switching-states, which increases the switching loss and decreases the efficiency. A five-level discontinuous pulse-width modulation(5L-DPWM) scheme with balanced DC-link capacitor voltages is proposed. Firstly, switching-state sequences and the subsector division are optimized. In each switching period, switching times are reduced by clamping the switching-state of one phase. DC-link capacitor voltage balancing constraints for different switching-state sequences under 5L-DPWM scheme are derived. These constraints are then combined with the volt-second balance equations to calculate the vector dwelling times, thereby balancing the DC-link capacitor voltages. Finally, a 9 kW three-phase five-level inverter experimental platform is built. Experimental results show that the proposed 5L-DPWM scheme can balance the DC-link capacitor voltage and reduce the switching times under various operating conditions. Compared with the existing carrier-overlapped PWM scheme, the proposed scheme improves efficiency by approximately 0.35% at the rated power.